Our new eighth-generation TPUs are designed to power the AI era.

Our new eighth-generation TPUs are designed to power the AI era.
Running millions of AI agents takes some serious computing muscle. Our AI Hypercomputer is a purpose-built system designed specifically for the massive scale of this new era, including the eighth generation of our custom TPU (Tensor Processing Unit) chips.
The TPU 8t is built to train AI models incredibly fast, while the TPU 8i is optimized for inference (actually serving up the models), delivering 80% better performance per dollar. We will also be among the first to offer the new NVIDIA Vera Rubin NVL72 systems, joining our existing lineup of NVIDIA GPUs and our super-efficient Google Cloud Axion processors.
To take advantage of this powerful compute, you need to move data at lightning speed. We unveiled the Virgo Network, a custom-built system to connect massive supercomputers, alongside storage breakthroughs like Managed Lustre, which can now move an incredible 10 terabytes of data per second.

The launch of the eighth-generation TPUs marks a major shift in how Google builds infrastructure, moving away from a “one-size-fits-all” chip to a dual-architecture strategy. Introduced at Google Cloud Next ’26, these chips are the foundation of what Google calls the “agentic era.”
For the first time, the lineup is bifurcated into two specialized designs:
1. TPU 8t (The Training Powerhouse)
Designed for massive-scale model pre-training, the TPU 8t (codenamed Sunfish) focuses on raw compute power and memory capacity.
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Scale: Can link up to 9,600 chips in a single superpod.
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Performance: Delivers nearly 3x the compute performance of the seventh-generation Ironwood.
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SparseCore: Includes a specialized accelerator to handle the irregular memory patterns of embedding lookups, which are common in modern large-scale models.
2. TPU 8i (The Inference & Reasoning Specialist)
The TPU 8i (codenamed Zebrafish) is engineered for “reasoning” and the high-throughput demands of running millions of AI agents.
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Low Latency: Designed to reduce network diameter by over 50%, ensuring rapid response times for interactive agents.
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SRAM Advantage: Features 3x more on-chip SRAM (384 MB) than prior generations to keep model data closer to the compute engine.
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Efficiency: Offers 80% better performance per dollar for inference compared to the previous generation.
Comparison at a Glance
| Feature | TPU 8t | TPU 8i |
| Primary Focus | Model Training | Inference & Reasoning |
| HBM Capacity | 216 GB | 288 GB |
| Network Topology | 3D Torus | Boardfly |
| Key Innovation | SparseCore (Embeddings) | CAE (Collectives Acceleration) |
| Host CPU | Arm-based Axion | Arm-based Axion |
The “Agentic” Shift
The split architecture is a direct response to the rise of AI Agents. While training still requires massive matrix multiplication (handled by the 8t), running an “agent” often involves complex reasoning and “Mixture of Experts” (MoE) models. These models require the lower latency and higher interconnect speeds found in the 8i’s Boardfly topology.
This generation also brings Native PyTorch support (TorchTPU), making it much easier for developers to bring existing models over from other hardware environments without major code rewrites.
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